The invention relates in general to the field of chip packaging, and in particular to methods for passive alignment of components of silicon photonics chips.
The optical coupling of light signals from/to photonic waveguides is an issue for optoelectronic (OE) chip packaging. High optical coupling efficiency, easy and low-cost OE chip assembly processes are often important requirements of such packaging. Another requirement is the integration of photonics with electronics, to further the scale of the off-chip Input/Output (I/O) bandwidth, while keeping low cost, area and power consumption. Silicon photonics in silicon-on-insulator (SOI) technology enables simultaneous realization of electrical and optical functions on the same chip.
Polymer waveguide (PWG) technology is known to provide satisfactory coupling into standard optical fibers. SOI and PWG cores are typically brought in contact and aligned horizontally.